| A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems M Hassan, H Patel, R Pellizzoni 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 307-316, 2015 | 77 | 2015 |
| Criticality-and requirement-aware bus arbitration for multi-core mixed criticality systems M Hassan, H Patel 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2016 | 57 | 2016 |
| Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems M Hassan, R Pellizzoni ACM SIGBED International Conference on Embedded Software (EMSOFT), ESWEEK, 2018 | 55 | 2018 |
| Evaporation estimation for Lake Nasser based on remote sensing technology M Hassan Ain Shams engineering journal 4 (4), 593-604, 2013 | 50 | 2013 |
| Predictable cache coherence for multi-core real-time systems M Hassan, AM Kaushik, H Patel 2017 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2017 | 41 | 2017 |
| Heterogeneous MPSoCs for mixed criticality systems: Challenges and opportunities M Hassan IEEE Design & Test 35 (4), 47-55, 2018 | 38 | 2018 |
| A Comparative Study of Predictable DRAM Controllers D GUo, M Hassan, R Pellizzoni, H Patel ACM Transactions on Embedded Computing Systems, 2017 | 38 | 2017 |
| Analysis of memory-contention in heterogeneous cots mpsocs M Hassan, R Pellizzoni 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020), 2020 | 36 | 2020 |
| On the off-chip memory latency of real-time systems: Is ddr dram really the best option? M Hassan 2018 IEEE Real-Time Systems Symposium (RTSS), 495-505, 2018 | 29 | 2018 |
| Designing predictable cache coherence protocols for multi-core real-time systems AM Kaushik, M Hassan, H Patel IEEE Transactions on Computers 70 (12), 2098-2111, 2020 | 27 | 2020 |
| PMC: A Requirement-Aware DRAM Controller for Multi-core Mixed Criticality Systems M Hassan, H Patel, R Pellizzoni ACM Transactions on Embedded Computing Systems (TECS), 2016 | 24 | 2016 |
| Reverse-engineering embedded memory controllers through latency-based analysis M Hassan, AM Kaushik, H Patel 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 297-306, 2015 | 24 | 2015 |
| Enabling predictable, simultaneous and coherent data sharing in mixed criticality systems N Sritharan, A Kaushik, M Hassan, H Patel 2019 IEEE Real-Time Systems Symposium (RTSS), 433-445, 2019 | 23 | 2019 |
| MCXplore: Automating the Validation Process of DRAM Memory Controller Designs M Hassan, H Patel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017 | 21 | 2017 |
| Discriminative coherence: Balancing performance and latency bounds in data-sharing multi-core real-time systems M Hassan 32nd Euromicro Conference on Real-Time Systems (ECRTS 2020), 2020 | 20 | 2020 |
| Mcsim: An extensible dram memory controller simulator R Mirosanlou, D Guo, M Hassan, R Pellizzoni IEEE Computer Architecture Letters 19 (2), 105-109, 2020 | 15 | 2020 |
| Drambulism: Balancing performance and predictability through dynamic pipelining R Mirosanlou, M Hassan, R Pellizzoni 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2020 | 13 | 2020 |
| The best of all worlds: Improving predictability at the performance of conventional coherence with no protocol modifications S Hessien, M Hassan 2020 IEEE Real-Time Systems Symposium (RTSS), 218-230, 2020 | 12 | 2020 |
| HourGlass: Predictable Time-based Cache Coherence Protocol for Mixed-Time Critical Multi-Cores H Sritharan, N., Kaushik, A., Hassan, Mohamed. and Patel https://ece.uwaterloo.ca/~m49hassa/publications/HourGlass_2017.pdf, 2017 | 11* | 2017 |
| Reduced latency DRAM for multi-core safety-critical real-time systems M Hassan Real-Time Systems 56 (2), 171-206, 2020 | 10 | 2020 |
Hiren PatelProfessor of Electrical and Computer Engineering, University of WaterlooVerified email at uwaterloo.ca
