Daniel Mueller-Gritschneder
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A successive approach to compute the bounded Pareto front of practical multiobjective optimization problems
D Mueller-Gritschneder, H Graeb, U Schlichtmann
SIAM Journal on Optimization 20 (2), 915-934, 2009
Safety evaluation of automotive electronics using virtual prototypes: State of the art and research challenges
JH Oetjens, N Bannow, M Becker, O Bringmann, A Burger, M Chaari, ...
Proceedings of the 51st annual design automation conference, 1-6, 2014
The next generation of virtual prototyping: Ultra-fast yet accurate simulation of HW/SW systems
O Bringmann, W Ecker, A Gerstlauer, A Goyal, D Mueller-Gritschneder, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
Signal processing strategies with the TDEMI measurement system
F Krug, D Mueller, P Russer
IEEE Transactions on Instrumentation and Measurement 53 (5), 1402-1408, 2004
Towards reliable and secure post-quantum co-processors based on RISC-V
T Fritzmann, U Sharif, D Müller-Gritschneder, C Reinbrecht, ...
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
Pareto optimization of analog circuits considering variability
H Graeb, D Mueller‐Gritschneder, U Schlichtmann
International journal of circuit theory and applications 37 (2), 283-299, 2009
A CPPLL hierarchical optimization methodology considering jitter, power and locking time
J Zou, D Mueller, H Graeb, U Schlichtmann
Proceedings of the 43rd annual Design Automation Conference, 19-24, 2006
Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience
A Herkersdorf, H Aliee, M Engel, M Glaß, C Gimmler-Dumont, J Henkel, ...
Microelectronics Reliability 54 (6-7), 1066-1074, 2014
Fully distributed deep learning inference on resource-constrained edge devices
R Stahl, Z Zhao, D Mueller-Gritschneder, A Gerstlauer, U Schlichtmann
Embedded Computer Systems: Architectures, Modeling, and Simulation: 19th …, 2019
DeeperThings: Fully distributed CNN inference on resource-constrained edge devices
R Stahl, A Hoffman, D Mueller-Gritschneder, A Gerstlauer, ...
International Journal of Parallel Programming 49, 600-624, 2021
A cross-layer technology-based study of how memory errors impact system resilience
VB Kleeberger, C Gimmler-Dumont, C Weis, A Herkersdorf, ...
IEEE Micro 33 (4), 46-55, 2013
Deterministic approaches to analog performance space exploration (PSE)
D Mueller, G Stehr, H Graeb, U Schlichtmann
Proceedings of the 42nd annual Design Automation Conference, 869-874, 2005
Trade-off design of analog circuits using goal attainment and" wave front" sequential quadratic programming
D Mueller, H Graeb, U Schlichtmann
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Automatic ILP-based firewall insertion for secure application-specific networks-on-chip
Y Hu, D Müller-Gritschneder, MJ Sepulveda, G Gogniat, U Schlichtmann
2015 Ninth International Workshop on Interconnection Network Architectures …, 2015
Control-flow-driven source level timing annotation for embedded software models on transaction level
D Mueller-Gritschneder, K Lu, U Schlichtmann
2011 14th Euromicro Conference on Digital System Design, 600-607, 2011
Computation of yield-optimized Pareto fronts for analog integrated circuit specifications
D Mueller-Gritschneder, H Graeb
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping
D Mueller-Gritschneder, K Devarajegowda, M Dittrich, W Ecker, M Greim, ...
Proceedings of the 28th International Symposium on Rapid System Prototyping …, 2017
Accurately timed transaction level models for virtual prototyping at high abstraction level
K Lu, D Müller-Gritschneder, U Schlichtmann
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 135-140, 2012
Deterministic synthesis of hybrid application-specific network-on-chip topologies
V Todorov, D Mueller-Gritschneder, H Reinig, U Schlichtmann
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014
Automated HW/SW co-design for edge AI: state, challenges and steps ahead
O Bringmann, W Ecker, I Feldner, A Frischknecht, C Gerum, ...
Proceedings of the 2021 International Conference on Hardware/Software …, 2021
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