| Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings XD Tan, CJR Shi, D Lungeanu, JC Lee, LP Yuan Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 78-83, 1999 | 184 | 1999 |
| Advanced model order reduction techniques in VLSI design S Tan, L He Cambridge University Press, 2007 | 175 | 2007 |
| Canonical symbolic analysis of large analog circuits with determinant decision diagrams CJR Shi, XD Tan IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000 | 171 | 2000 |
| Pathological element-based active device models and their application to symbolic analysis C Sánchez-López, FV Fernández, E Tlelo-Cuautle, SXD Tan IEEE Transactions on Circuits and Systems I: Regular Papers 58 (6), 1382-1395, 2011 | 142 | 2011 |
| Physics-based electromigration assessment for power grid networks X Huang, T Yu, V Sukharev, SXD Tan Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 123 | 2014 |
| Fast power/ground network optimization based on equivalent circuit modeling XDS Tan, CJR Shi Proceedings of the 38th annual Design Automation Conference, 550-554, 2001 | 102 | 2001 |
| A systematic method for functional unit power estimation in microprocessors W Wu, L Jin, J Yang, P Liu, SXD Tan Proceedings of the 43rd annual Design Automation Conference, 554-557, 2006 | 96 | 2006 |
| Compact representation and efficient generation of s-expanded symbolic network functions for computer-aided analog circuit design CJR Shi, XD Tan IEEE Transactions on computer-aided design of integrated circuits and …, 2001 | 87 | 2001 |
| Dynamic FPGA routing for just-in-time FPGA compilation R Lysecky, F Vahid, SXD Tan Proceedings of the 41st annual design automation conference, 954-959, 2004 | 86 | 2004 |
| Design of analog circuits through symbolic analysis M Fakhfakh, E Tlelo-Cuautle, FV Fernández Bentham Science Publishers, 2012 | 83 | 2012 |
| Hierarchical symbolic analysis of analog integrated circuits via determinant decision diagrams XD Tan, CJR Shi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2000 | 74 | 2000 |
| Physics-based electromigration models and full-chip assessment for power grid networks X Huang, A Kteyan, SXD Tan, V Sukharev IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 65 | 2016 |
| Fast thermal simulation for architecture level dynamic thermal management P Liu, Z Qi, H Li, L Jin, W Wu, SXD Tan, J Yang ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 60 | 2005 |
| GPU-accelerated parallel sparse LU factorization method for fast circuit analysis K He, SXD Tan, H Wang, G Shi IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (3 …, 2015 | 58 | 2015 |
| GPU friendly fast Poisson solver for structured power grid network analysis J Shi, Y Cai, W Hou, L Ma, SXD Tan, PH Ho, X Wang 2009 46th ACM/IEEE Design Automation Conference, 178-183, 2009 | 58 | 2009 |
| Symbolic analysis of analog circuits containing voltage mirrors and current mirrors E Tlelo-Cuautle, C Sánchez-López, E Martinez-Romero, SXD Tan Analog Integrated Circuits and Signal Processing 65 (1), 89-95, 2010 | 57 | 2010 |
| Partitioning-based approach to fast on-chip decap budgeting and minimization H Li, Z Qi, SXD Tan, L Wu, Y Cai, X Hong Proceedings of the 42nd annual Design Automation Conference, 170-175, 2005 | 52 | 2005 |
| Efficient power modeling and software thermal sensing for runtime temperature monitoring W Wu, L Jin, J Yang, P Liu, SXD Tan ACM Transactions on Design Automation of Electronic Systems (TODAES) 12 (3 …, 2008 | 51 | 2008 |
| A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery J Fu, Z Luo, X Hong, Y Cai, SXD Tan, Z Pan IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2004 | 51 | 2004 |
| Analytical modeling and characterization of electromigration effects for multibranch interconnect trees HB Chen, SXD Tan, X Huang, T Kim, V Sukharev IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 48 | 2016 |
Hao Yu （余浩）SUSTech（南方科技大学）Verified email at sustech.edu.cn
