Lucas Klemmer
Cited by
Cited by
WAL: A Novel Waveform Analysis Language for Advanced Design Understanding and Debugging
L Klemmer, D Große
2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC), 358-364, 2022
EPEX: Processor Verification by Equivalent Program Execution
L Klemmer, D Große
Proceedings of the 2021 on Great Lakes Symposium on VLSI, 33-38, 2021
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle
L Klemmer, D Große
2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 38-43, 2022
Waveform-based performance analysis of RISC-V processors: late breaking results
L Klemmer, D Große
Proceedings of the 59th ACM/IEEE Design Automation Conference, 1404-1405, 2022
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding
L Klemmer, S Froehlich, R Drechsler, D Große
2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021
Formal Verification of SUBLEQ Microcode implementing the RV32I ISA
L Klemmer, S Gurtner, D Große
2022 Forum on Specification & Design Languages (FDL), 1-8, 2022
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks
S Froehlich, L Klemmer, D Große, R Drechsler
2020 IEEE 50th International Symposium on Multiple-Valued Logic (ISMVL), 64-69, 2020
Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis
F Skarman, L Klemmer, O Gustafsson, D Große
2023 Forum on Specification & Design Languages (FDL), 1-8, 2023
RVVRadar: A Framework for Supporting the Programmer in Vectorization for RISC-V
L Klemmer, M Schlägl, D Große
Proceedings of the Great Lakes Symposium on VLSI 2022, 183-187, 2022
Towards a Highly Interactive Design-Debug-Verification Cycle
LK Daniel, D Große
2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC), 692-697, 2024
Large-scale Gatelevel Optimization Leveraging Property Checking
L Klemmer, D Bonora, D Große
DVCon Europe, 2023
WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL
L Klemmer, D Große
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
Programming Language Assisted Waveform Analysis: A Case Study on the Instruction Performance of SERV
L Klemmer, D Große
arXiv preprint arXiv:2304.05837, 2023
Using Formal Verification Methods for Optimization of Circuits under External Constraints
D Große, L Klemmer, D Bonora
WSVA: A SystemVerilog Assertion to WAL Compiler
L Klemmer, D Große
Replacing RISC-V Instructions by Others
S Gurtner, L Klemmer, M Fleury, D Große
A DSL for Visualizing Pipelines: A RISC-V Case Study
L Klemmer, D Große
How We Learned to Stop Worrying and Build a RISC-V VP with only one Microcode Instruction
L Klemmer, S Gurtner, D Große
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