Amirali Boroumand
Amirali Boroumand
Verified email at cmu.edu
TitleCited byYear
Ambit: In-memory accelerator for bulk bitwise operations using commodity DRAM technology
V Seshadri, D Lee, T Mullins, H Hassan, A Boroumand, J Kim, MA Kozuch, ...
Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017
1102017
Fast bulk bitwise AND and OR in DRAM
V Seshadri, K Hsieh, A Boroum, D Lee, MA Kozuch, O Mutlu, PB Gibbons, ...
IEEE Computer Architecture Letters 14 (2), 127-131, 2015
1062015
Accelerating pointer chasing in 3D-stacked memory: Challenges, mechanisms, evaluation
K Hsieh, S Khan, N Vijaykumar, KK Chang, A Boroumand, S Ghose, ...
2016 IEEE 34th International Conference on Computer Design (ICCD), 25-32, 2016
832016
LazyPIM: An efficient cache coherence mechanism for processing-in-memory
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, K Hsieh, KT Malladi, ...
IEEE Computer Architecture Letters 16 (1), 46-50, 2016
792016
Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses
V Seshadri, T Mullins, A Boroumand, O Mutlu, PB Gibbons, MA Kozuch, ...
Proceedings of the 48th International Symposium on Microarchitecture, 267-280, 2015
742015
Google workloads for consumer devices: Mitigating data movement bottlenecks
A Boroumand, S Ghose, Y Kim, R Ausavarungnirun, E Shiu, R Thakur, ...
ACM SIGPLAN Notices 53 (2), 316-331, 2018
492018
Buddy-ram: Improving the performance and efficiency of bulk bitwise operations using DRAM
V Seshadri, D Lee, T Mullins, H Hassan, A Boroumand, J Kim, MA Kozuch, ...
arXiv preprint arXiv:1611.09988, 2016
272016
Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions
S Ghose, K Hsieh, A Boroumand, R Ausavarungnirun, O Mutlu
arXiv preprint arXiv:1802.00320, 2018
182018
The processing-in-memory paradigm: Mechanisms to enable adoption
S Ghose, K Hsieh, A Boroumand, R Ausavarungnirun, O Mutlu
Beyond-CMOS Technologies for Next Generation Computer Design, 133-194, 2019
112019
Using ECC DRAM to adaptively increase memory capacity
Y Luo, S Ghose, T Li, S Govindan, B Sharma, B Kelly, A Boroumand, ...
arXiv preprint arXiv:1706.08870, 2017
92017
LazyPIM: Efficient Support for Cache Coherence in Processing-in-Memory Architectures
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, N Hajinazar, ...
arXiv preprint arXiv:1706.03162, 2017
82017
CoNDA: Enabling efficient near-data accelerator communication by optimizing data movement
A Boroumand, S Ghose, M Patel, R Ausavarungnirun, H Hassan, B Lucia, ...
ISCA, 2019
52019
CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators
A Boroumand, S Ghose, M Patel, H Hassan, B Lucia, R Ausavarungnirun, ...
52019
A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure
M Arjomand, A Boroumand, H Sarbazi-Azad
Computers & Electrical Engineering 40 (1), 158-167, 2014
52014
Processing-in-Memory: A Workload-Driven Perspective
S Ghose, A Boroumand, J Kim, J Gómez-Luna, O Mutlu
IBM Journal of Research and Development, 2019
2019
A Workload and Programming Ease Driven Perspective of Processing-in-Memory
S Ghose, A Boroumand, JS Kim, J Gómez-Luna, O Mutlu
arXiv preprint arXiv:1907.12947, 2019
2019
Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study
M Momtazpour, O Assare, N Rahmati, A Boroumand, S Barati, M Goudarzi
IET Computers & Digital Techniques 9 (4), 221-229, 2015
2015
2017 Index IEEE Computer Architecture Letters Vol. 16
N Abu-Ghazaleh, A Adileh, A Agrawal, H Ahmadvand, JH Ahn, ...
MiCRo 50 Author index
A Jaleel, AJ Elmore, A Bhattacharjee, A Holmes, AJ McPadden, ...
Yield-Driven Design-Time Task Scheduling Techniques for MPSoCs under Process Variation: A Comparative Study
M Momtazpour, O Assare, N Rahmati, A Boroumand, S Barati, M Goudarzi
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Articles 1–20