Nagarajan Ranganathan
Nagarajan Ranganathan
Distinguished University Professor of Computer Science and Engineering, University of South Florida
Verified email at - Homepage
Cited by
Cited by
Gabor filter-based edge detection
R Mehrotra, KR Namuduri, N Ranganathan
Pattern recognition 25 (12), 1479-1494, 1992
Composable lightweight processors
C Kim, S Sethumadhavan, MS Govindan, N Ranganathan, D Gulati, ...
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
Distributed microarchitectural protocols in the TRIPS prototype processor
K Sankaralingam, R Nagarajan, R McDonald, R Desikan, S Drolia, ...
2006 39th Annual IEEE/ACM International Symposium on Microarchitecture …, 2006
LECTOR: a technique for leakage reduction in CMOS circuits
N Hanchate, N Ranganathan
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12 (2), 196-205, 2004
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs
H Thapliyal, N Ranganathan
ACM Journal on Emerging Technologies in Computing Systems (JETC) 6 (4), 1-31, 2010
Reversible logic-based concurrently testable latches for molecular QCA
H Thapliyal, N Ranganathan
IEEE transactions on nanotechnology 9 (1), 62-69, 2009
JAGUAR: A fully pipelined VLSI architecture for JPEG image compression standard
M Kovac, N Ranganathan
Proceedings of the IEEE 83 (2), 247-258, 1995
Corner detection
R Mehrotra, S Nichani, N Ranganathan
Pattern recognition 23 (11), 1223-1233, 1990
Design of efficient reversible binary subtractors based on a new reversible gate
H Thapliyal, N Ranganathan
2009 IEEE computer society annual symposium on VLSI, 229-234, 2009
Design of testable reversible sequential circuits
H Thapliyal, N Ranganathan, S Kotiyal
IEEE transactions on very large scale integration (VLSI) systems 21 (7 …, 2012
Development of through silicon via (TSV) interposer technology for large die (21ื 21mm) fine-pitch Cu/low-k FCBGA package
X Zhang, TC Chai, JH Lau, CS Selvanayagam, K Biswas, S Liu, D Pinjala, ...
2009 59th Electronic components and technology conference, 305-312, 2009
Design of a reversible ALU based on novel programmable reversible logic gate structures
M Morrison, N Ranganathan
2011 IEEE computer society annual symposium on VLSI, 126-131, 2011
Low-power high-level synthesis for nanoscale CMOS circuits
SP Mohanty, N Ranganathan, E Kougianos, P Patra
Springer Science & Business Media, 2008
High-speed VLSI designs for Lempel-Ziv-based data compression
N Ranganathan, S Henriques
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 1993
Efficient VLSI designs for data transformation of tree-based codes
A Mukherjee, N Ranganathan, M Bassiouni
IEEE transactions on circuits and systems 38 (3), 306-314, 1991
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP
K Sankaralingam, R Nagarajan, H Liu, C Kim, J Huh, N Ranganathan, ...
ACM Transactions on Architecture and Code Optimization (TACO) 1 (1), 62-93, 2004
Method and apparatus for the compression and decompression of data using Lempel-Ziv based techniques
N Ranganathan, S Henriques
US Patent 5,179,378, 1993
VLSI implementation of invisible digital watermarking algorithms towards the development of a secure JPEG encoder
SP Mohanty, N Ranganathan, RK Namballa
2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No. 03TH8682 …, 2003
Design of reversible latches optimized for quantum cost, delay and garbage outputs
H Thapliyal, N Ranganathan
2010 23rd International Conference on VLSI Design, 235-240, 2010
Improving accuracy in Mitchell's logarithmic multiplication using operand decomposition
V Mahalingam, N Ranganathan
IEEE Transactions on Computers 55 (12), 1523-1535, 2006
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