Wire-aware architecture and dataflow for cnn accelerators S Gudaparthi, S Narayanan, R Balasubramonian, E Giacomin, ... Proceedings of the 52nd annual ieee/acm international symposium on …, 2019 | 44 | 2019 |
CANDLES: Channel-aware novel dataflow-microarchitecture co-design for low energy sparse neural network acceleration S Gudaparthi, S Singh, S Narayanan, R Balasubramonian, V Sathe 2022 IEEE International Symposium on high-performance computer architecture …, 2022 | 10 | 2022 |
A multiply-and-accumulate array for machine learning applications based on a 3D nanofabric flow E Giacomin, S Gudaparthi, J Boemmels, R Balasubramonian, F Catthoor, ... IEEE Transactions on Nanotechnology 20, 873-882, 2021 | 5 | 2021 |
Selective register-file cache: an energy saving technique for embedded processor architecture S Gudaparthi, R Shrestha Design Automation for Embedded Systems 26 (2), 105-124, 2022 | 3 | 2022 |
Moving CNN accelerator computations closer to data S Gudaparthi, S Narayanan, R Balasubramonian 2018 1st Workshop on Energy Efficient Machine Learning and Cognitive …, 2018 | 1 | 2018 |
Pathfinder: Practical Real-Time Learning for Data Prefetching L Jia, JP Mcmahon, S Gudaparthi, S Singh, R Balasubramonian Proceedings of the 29th ACM International Conference on Architectural …, 2024 | | 2024 |
Hyena: Balancing Packing, Reuse, and Rotations for Encrypted Inference S Singh, S Singh, S Gudaparthi, X Fan, R Balasubramonian 2024 IEEE Symposium on Security and Privacy (SP), 107-107, 2024 | | 2024 |
Tensor Acceleration for Non-Conventional Applications Using Versatile Integrants S Gudaparthi The University of Utah, 2022 | | 2022 |
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization S Gudaparthi, R Shrestha VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee …, 2017 | | 2017 |
Aleksic, Mickey 14 Balasubramonian, Rajeev 4, 34 Chai, Sek 29 Culurciello, Eugenio 9, 24 SH Fatemi Langroudi, C Feng, G Fursin, V Gokhale, S Gudaparthi, ... | | |