| Understanding reduced-voltage operation in modern dram devices: Experimental characterization, analysis, and mechanisms KK Chang, AG Yaălikçi, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 1 (1 …, 2017 | 132 | 2017 |
| Runnemede: An Architecture for Ubiquitous High-Performance Computing NP Carter, A Agrawal, S Borkar, R Cledat, H David, D Dunning, J Fryman, ... High Performance Computer Architecture (HPCA) 2013, 2013 | 120 | 2013 |
| Fine-Grained DRAM: Energy-Efficient DRAM for Extreme Bandwidth Systems M O’Connor, N Chatterjee, D Lee, J Wilson, A Agrawal, SW Keckler, ... International Symposium on Microarchitecture (MICRO) 2017, 2017 | 89 | 2017 |
| Mosaic: Exploiting the Spatial Locality of Process Variation to Reduce Refresh Energy in On-Chip eDRAM Modules A Agrawal, A Ansari, J Torrellas High Performance Computer Architecture (HPCA) 2014, 2014 | 68 | 2014 |
| What your DRAM power models are not telling you: Lessons from a detailed experimental study S Ghose, AG Yaglikçi, R Gupta, D Lee, K Kudrolli, WX Liu, H Hassan, ... Proceedings of the ACM on Measurement and Analysis of Computing Systems 2 (3 …, 2018 | 64 | 2018 |
| Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies A Agrawal, P Jain, A Ansari, J Torrellas High Performance Computer Architecture (HPCA) 2013, 2013 | 55 | 2013 |
| Exposing control of power and clock gating for software NP Carter, JB Fryman, RC Knauerhase, A Agrawal, J Torrellas US Patent App. 13/630,738, 2012 | 29 | 2012 |
| Xylem: Enhancing Vertical Thermal Conduction in 3D Processor-Memory Stacks A Agrawal, J Torrellas, S Idgunji International Symposium on Microarchitecture (MICRO) 2017, 2017 | 24 | 2017 |
| ScalCore: Designing a core for voltage scalability B Gopireddy, C Song, J Torrellas, NS Kim, A Agrawal, A Mishra High Performance Computer Architecture (HPCA) 2016, 2016 | 17 | 2016 |
| Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization KK Chang, AG Yaglikci, A Agrawal, N Chatterjee, S Ghose, A Kashyap, ... Analysis, and Mechanisms. In SIGMETRICS 3 (5.5), 3.5, 2017 | 16 | 2017 |
| Survive: Pointer-based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery A Mirhosseini, A Agrawal, J Torrellas IEEE Computer Architecture Letters (CAL), 2016 | 16 | 2016 |
| CLARA: Circular Linked-List Auto and Self Refresh Architecture A Agrawal, M O'Connor, E Bolotin, N Chatterjee, J Emer, S Keckler International Symposium on Memory Systems (MEMSYS) 2016, 2016 | 7 | 2016 |
| Method and apparatus for dishonest hardware policies J Fryman, N Carter, R Knauerhase, S Schoenberg, A Agrawal US Patent 8,935,775, 2015 | 6 | 2015 |
| Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency KK Chang, AG Yaglıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... arXiv preprint arXiv:1805.03175, 2018 | 5 | 2018 |
| Snatch: Opportunistically Reassigning Power Allocation between Processor and Memory in 3D Stacks D Skarlatos, R Thomas, A Agrawal, S Qin, R Pilawa-Podgurski, ... International Symposium on Microarchitecture (MICRO) 2016, 2016 | 5 | 2016 |
| Robust method for integration of bump cells in semiconductor device design L Hung-Yi, CH Wang, A Agrawal US Patent 8,239,802, 2012 | 5 | 2012 |
| Understanding Reduced-Voltage Operation in Modern DRAM Chips: Characterization, Analysis, and Mechanisms KK Chang, AG Yağlıkçı, S Ghose, A Agrawal, N Chatterjee, A Kashyap, ... arXiv preprint arXiv:1705.10292, 2017 | 3 | 2017 |
| Refresh Reduction In Dynamic Memories A Agrawal University of Illinois Urbana Champaign, 2014 | 3 | 2014 |
Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-ChampaignVerified email at illinois.edu
