Abdulkadir Utku Diril
Abdulkadir Utku Diril
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Title
Cited by
Cited by
Year
Soft-error tolerance analysis and optimization of nanometer circuits
YS Dhillon, AU Diril, A Chatterjee
Design, Automation, and Test in Europe, 389-400, 2008
1582008
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
YS Dhillon, AU Diril, A Chatterjee, AD Singh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (5), 514-524, 2006
1052006
Algorithm for achieving minimum energy consumption in CMOS circuits using multiple supply and threshold voltages at the module level
YS Dhillon, AU Diril, A Chatterjee, HHS Lee
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
502003
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
AU Diril, YS Dhillon, A Chatterjee, AD Singh
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (9 …, 2005
402005
Load and logic co-optimization for design of soft-error resistant nanometer CMOS circuits
YS Dhillon, AU Diril, A Chatterjee, C Metra
11th IEEE International On-Line Testing Symposium, 35-40, 2005
272005
Design of adaptive nanometer digital systems for effective control of soft error tolerance
AU Diril, YS Dhillon, A Chatterjee, AD Singh
23rd IEEE VLSI Test Symposium (VTS'05), 298-303, 2005
262005
Power estimation based on block activity
H Cha, RJ Hasslen III, JA Robinson, SJ Treichler, AU Diril
US Patent 8,060,765, 2011
252011
Sizing CMOS circuits for increased transient error tolerance
YS Dhillon, AU Diril, A Chatterjee, AD Singh
Proceedings. 10th IEEE International On-Line Testing Symposium, 11-16, 2004
252004
The elusive metric for low-power architecture research
HHS Lee, JB Fryman, AU Diril, YS Dhillon
Proceedings of the Workshop on Complexity-Effective Design, 2003
182003
Adaptive design for performance-optimized robustness
R Datta, JA Abraham, AU Diril, A Chatterjee, K Nowka
2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2006
122006
Probabilistic self-adaptation of nanoscale CMOS circuits: yield maximization under increased intra-die variations
M Ashouei, MM Nisar, A Chatterjee, AD Singh, AU Diril
20th International Conference on VLSI Design held jointly with 6th …, 2007
112007
An o (n) supply voltage assignment algorithm for low-energy serially connected cmos modules and a heuristic extension to acyclic data flow graphs
AU Diril, YS Dhillon, K Choi, A Chatterjee
IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 173-179, 2003
72003
Efficient tile-based rasterization
AU Diril, F Garritsen
US Patent 8,416,241, 2013
62013
Low-power domino circuits using NMOS pull-up on off-critical paths
AU Diril, YS Dhillon, A Chatterjee, AD Singh
Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation …, 2005
52005
Thin-line detection apparatus and method
L Zhong, AU Diril
US Patent 8,553,046, 2013
42013
Circuit level techniques for power and reliability optimization of CMOS logic
AU Diril
Georgia Institute of Technology, 2005
32005
Low-power dual Vth pseudo dual Vdd domino circuits
YS Dhillon, AU Diril, A Chatterjee, AD Singh
Proceedings of the 17th symposium on Integrated Circuits and System Design …, 2004
32004
Processed texel cache
J Wang, AU Diril
US Patent 9,600,909, 2017
12017
Global co-op: Engineering education through outsourcing
O Ergin, AU Diril, WJ Dai
2012 2nd Interdisciplinary Engineering Design Education Conference (IEDEC …, 2012
12012
Pseudo Dual Supply Voltage Domino Logic Design
AU Diril, YS Dhillon, A Chatterjee, AD Singh
Journal of Low Power Electronics 1 (2), 145-152, 2005
12005
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