| ESD protection for mixed-voltage I/O using NMOS transistors stacked in a cascode configuration WR Anderson, DB Krakauer Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1998 …, 1998 | 101 | 1998 |
| ESD protection in a 3.3 V sub-micron silicided CMOS technology D Krakauer Journal of electrostatics 31 (2-3), 111-129, 1993 | 55 | 1993 |
| Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps DB Krakauer, K Mistry, S Butler, H Partovi US Patent 5,617,283, 1997 | 54 | 1997 |
| ESD protection clamp for mixed voltage I/O stages using NMOS transistors DB Krakauer US Patent 5,932,918, 1999 | 44 | 1999 |
| SPICE model and parameters for fully-depleted SOI MOSFET's including self-heating LT Su, DA Antoniadis, ND Arora, BS Doyle, DB Krakauer IEEE Electron device letters 15 (10), 374-376, 1994 | 42 | 1994 |
| Impact of snapback-induced hole injection on gate oxide reliability of N-MOSFETs KR Mistry, DB Krakauer, BS Doyle IEEE electron device letters 11 (10), 460-462, 1990 | 36 | 1990 |
| ELECTRON DEVICE LT Su, DA Antoniadis, ND Arora, BS Doyle, DB Krakauer, C Tedesco, ... | 33 | 2005 |
| Electro-static discharge protection device having a modulated control input terminal H Partovi, KR Mistry, DB Krakauer, WA McGee US Patent 6,078,487, 2000 | 32 | 2000 |
| Measurement of very low tunneling current density in SiO/sub 2/using the floating-gate technique B Fishbein, D Krakauer, B Doyle IEEE electron device letters 12 (12), 713-715, 1991 | 27 | 1991 |
| Examination of oxide damage during high-current stress of n-MOS transistors BS Doyle, DB Krakauer, KR Mistry IEEE Transactions on electron Devices 40 (5), 980-985, 1993 | 24 | 1993 |
| ESD protection clamp for mixed voltage I/O stages using NMOS transistors DB Krakauer US Patent 5,780,897, 1998 | 22 | 1998 |
| On latency and the physical mechanisms underlying gate oxide damage during ESD events in n-channel MOSFETs DB Krakauer, KR Mistry EOS/ESD Symposium Proceedings, 121-126, 1989 | 22 | 1989 |
| Circuit interactions during electrostatic discharge D Krakauer, K Mistry, H Partovi ELECTRICAL OVERSTRESS ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, 113-113, 1994 | 17 | 1994 |
| ESD protection clamp for mixed voltage I/O stages using NMOS transistors DB Krakauer US Patent 6,097,071, 2000 | 13 | 2000 |
| Transistor hot carrier reliability assurance in CMOS technologies DB Jackson, DA Bell, BS Doyle, BJ Fishbein, DB Krakauer Digital Technical Journal 4, 100-100, 1992 | 7 | 1992 |
| ESD protection for mixed-voltage I W Anderson, D Krakauer O Using NMOS Transistors Stacked in Cascode Configuration, Electrical …, 1998 | 5 | 1998 |
| EOS/ESD Symposium Proceedings B Anderson, DB Krakauer ESD Symposium Proceedings, 199-203, 1991 | 5 | 1991 |
| Dependence of input ESD failure thresholds on IC design style K Mistry, D Krakauer, R Titus Proc. 12th EOS/ESD Symp., 214-217, 1990 | 4 | 1990 |
| An in-process monitor for n-channel MOSFET hot carrier lifetimes KR Mistry, DB Krakauer, BS Doyle, TA Spooner, DB Jackson 30th Annual Proceedings Reliability Physics 1992, 116-121, 1992 | 2 | 1992 |
| Identification and localisation of gate oxide weaknesses in n-MOS transistors through Fowler-Nordheim tunnelling and SPICE simulation D Krakauer, BS Doyle Electronics Letters 26 (4), 230-231, 1990 | | 1990 |
