| T. Huynh-The S Wang, MA Qureshi, L Miralles-Pechuaán arXiv preprint arXiv:2112.04698, 2021 | 33 | 2021 |
| Huynh-The, T.; Gadekallu S Wang, MA Qureshi, L Miralles-Pechuaán arXiv preprint arXiv:2112.04698, 2021 | 16 | 2021 |
| A restore-free mode for MLC STT-RAM caches MA Qureshi, H Kim, S Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (6 …, 2019 | 15 | 2019 |
| Huynh-The T S Wang, MA Qureshi, L Miralles-Pechuaán arXiv preprint arXiv:2112.04698, 2021 | 14 | 2021 |
| SALE: smartly allocating low-cost many-bit ECC for mitigating read and write errors in STT-RAM caches MA Qureshi, J Park, S Kim IEEE transactions on very large scale integration (VLSI) systems 28 (6 …, 2020 | 7 | 2020 |
| Reliable Spin-Transfer Torque RAM (STT-RAM) caches for low energy consumption and performance overheads MA Qureshi 한국과학기술원, 2020 | | 2020 |
| Memory Circuits A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines..................... L Lu, T Yoo, VL Le, TTH Kim, MA Qureshi, J Park, S Kim, C McCullough, ... | | |
