| LeFlow: Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks DH Noronha, B Salehpour, SJE Wilton FSP Workshop 2018; Fifth International Workshop on FPGAs for Software …, 2018 | 83 | 2018 |
| A parallel implementation of sequential minimal optimization on FPGA DH Noronha, MF Torquato, MAC Fernandes Microprocessors and Microsystems 69, 138-151, 2019 | 31 | 2019 |
| On-chip FPGA debug instrumentation for machine learning applications D Holanda Noronha, R Zhao, J Goeders, W Luk, SJE Wilton Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 23 | 2019 |
| Proposal of the tactile glove device JCVS Junior, MF Torquato, DH Noronha, SN Silva, MAC Fernandes Sensors 19 (22), 5029, 2019 | 18 | 2019 |
| An overlay for rapid fpga debug of machine learning applications DH Noronha, R Zhao, Z Que, J Goeders, W Luk, S Wilton 2019 International Conference on Field-Programmable Technology (ICFPT), 135-143, 2019 | 10 | 2019 |
| Leflow: Automatic compilation of tensorflow machine learning applications to fpgas DH Noronha, K Gibson, B Salehpour, SJE Wilton 2018 International Conference on Field-Programmable Technology (FPT), 393-396, 2018 | 10 | 2018 |
| Kibo: An open-source fixed-point tool-kit for training and inference in FPGA-based deep learning networks DH Noronha, PHW Leong, SJE Wilton 2018 IEEE International Parallel and Distributed Processing Symposium …, 2018 | 8 | 2018 |
| Flexible instrumentation for live on-chip debug of machine learning training on FPGAs DH Noronha, Z Que, W Luk, SJE Wilton 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 5 | 2021 |
| Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs K Gibson, E Roorda, DH Noronha, S Wilton 2020 30th International Conference on Field-Programmable Logic and …, 2020 | 5 | 2020 |
| Rapid circuit-specific inlining tuning for FPGA high-level synthesis DH Noronha, JP Pinilla, SJE Wilton 2017 International Conference on ReConFigurable Computing and FPGAs …, 2017 | 5 | 2017 |
| Towards in-circuit tuning of deep learning designs Z Que, DH Noronha, R Zhao, SJE Wilton, W Luk 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-6, 2019 | 2 | 2019 |
| Boosting domain-specific debug through inter-frame compression Z Nafziger, M Chua, DH Noronha, SJE Wilton 2022 International Conference on Field-Programmable Technology (ICFPT), 1-10, 2022 | 1 | 2022 |
| Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs Z Que, DH Noronha, R Zhao, X Niu, SJE Wilton, W Luk 2020 International Conference on Field-Programmable Technology (ICFPT), 301-301, 2020 | 1 | 2020 |
| Adaptive Clock Management of HLS-generated Circuits on FPGAs K Gibson, E Roorda, DH Noronha, SJE Wilton ACM Transactions on Reconfigurable Technology and Systems 15 (4), 1-32, 2022 | | 2022 |
| In-circuit tuning of deep learning designs Z Que, DH Noronha, R Zhao, X Niu, SJE Wilton, W Luk Journal of Systems Architecture 118, 102198, 2021 | | 2021 |
| 1A. 1-An All-Digital True Random Number Generator Based on Chaotic Cellular Automata Topology Scott Best, Xiaolin Xu 1A. 2-SCR-QRNG: Side-Channel Resistant Design using Quantum … J Park, S Cho, T Lim, S Bhunia, M Tehranipoor, Z Wu, H Patel, M Sachdev, ... | | 2019 |
| ZHW: A Numerical CODEC for Big Data Scientific Computation........................ 56 Michael Barrow, Zhuanhao Wu, Scott Lloyd, Maya Gokhale, Hiren Patel and Peter Lindstrom … Z Nafziger, M Chua, DH Noronha, SJE Wilton, J Soundarya, B Zhang, ... | | |
