| Synthesis of reversible sequential elements ML Chuang, CY Wang ACM Journal on Emerging Technologies in Computing Systems (JETC) 3 (4), 1-19, 2008 | 113 | 2008 |
| Automated mapping for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 878-883, 2011 | 28 | 2011 |
| On automatic-verification pattern generation for SoC with port-order fault model CY Wang, SW Tung, JY Jou IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002 | 25 | 2002 |
| Fast detection of node mergers using logic implications YC Chen, CY Wang Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 22 | 2009 |
| A synthesis algorithm for reconfigurable single-electron transistor arrays YC Chen, S Eachempati, CY Wang, S Datta, Y Xie, V Narayanan ACM Journal on Emerging Technologies in Computing Systems (JETC) 9 (1), 1-20, 2013 | 21 | 2013 |
| Fast node merging with don't cares using logic implications YC Chen, CY Wang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 21 | 2010 |
| On rewiring and simplification for canonicity in threshold logic circuits PY Kuo, CY Wang, CY Huang 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 396-403, 2011 | 19 | 2011 |
| On reconfigurable single-electron transistor arrays synthesis using reordering techniques CE Chiang, LF Tang, CY Wang, CY Huang, YC Chen, S Datta, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 18 | 2013 |
| Node addition and removal in the presence of don't cares YC Chen, CY Wang Proceedings of the 47th Design Automation Conference, 505-510, 2010 | 17 | 2010 |
| A bus-encoding scheme for crosstalk elimination in high-performance processor design WW Hsieh, PY Chen, CY Wang, TT Hwang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 15 | 2007 |
| Verification of reconfigurable binary decision diagram-based single-electron transistor arrays YC Chen, CY Wang, CY Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 13 | 2013 |
| Rewiring using IRredundancy removal and addition CC Lin, CY Wang 2009 Design, Automation & Test in Europe Conference & Exhibition, 324-327, 2009 | 13 | 2009 |
| Rewiring for threshold logic circuit minimization CC Lin, CY Wang, YC Chen, CY Huang 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014 | 12 | 2014 |
| Logic Restructuring Using Node Addition and Removal YC Chen, CY Wang Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2012 | 12 | 2012 |
| On synthesizing memristor-based logic circuits with minimal operational pulses HP Wang, CC Lin, CC Wu, YC Chen, CY Wang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (12 …, 2018 | 11 | 2018 |
| Width minimization in the single-electron transistor array synthesis CW Liu, CE Chiang, CY Huang, CY Wang, YC Chen, S Datta, ... 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014 | 11 | 2014 |
| A Probabilistic Analysis Method for Functional Qualification under Mutation Analysis HY Lin, CY Wang, SC Chang, YC Chen, HM Chou, CY Huang, YC Yang, ... Design, Automation and Test in Europe, 147-152, 2012 | 11 | 2012 |
| A novel ACO-based pattern generation for peak power estimation in VLSI circuits YL Liu, CY Wang, YC Chen, YH Chang 2009 10th International Symposium on Quality Electronic Design, 317-323, 2009 | 10 | 2009 |
| BDD-based synthesis of reconfigurable single-electron transistor arrays Z Zhao, CW Liu, CY Wang, W Qian 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 47-54, 2014 | 9 | 2014 |
| An AVPG for SoC design verification with port order fault model CY Wang, SW Tung, JY Jou ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems …, 2001 | 9 | 2001 |
