Haoxing Ren (Mark)
Haoxing Ren (Mark)
Verified email at nvidia.com - Homepage
Title
Cited by
Cited by
Year
Sensitivity guided net weighting for placement driven synthesis
TY Wang, JL Tsai, CCP Chen
Proceedings of the 2004 international symposium on Physical design, 124-131, 2004
852004
Relative ordering circuit synthesis
M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler
US Patent 8,756,541, 2014
812014
RQL: Global placement via relaxed quadratic spreading and linearization
N Viswanathan, GJ Nam, CJ Alpert, P Villarrubia, H Ren, C Chu
Proceedings of the 44th annual Design Automation Conference, 453-458, 2007
812007
Techniques for fast physical synthesis
CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ...
Proceedings of the IEEE 95 (3), 573-599, 2007
812007
Diffusion-based placement migration
H Ren, DZ Pan, CJ Alpert, P Villarrubia
Proceedings of the 42nd annual Design Automation Conference, 515-520, 2005
802005
DeltaSyn: An efficient logic difference optimizer for ECO synthesis
S Krishnaswamy, H Ren, N Modi, R Puri
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
582009
RouteNet: Routability prediction for mixed-size designs using convolutional neural network
Z Xie, YH Huang, GQ Fang, H Ren, SY Fang, Y Chen, J Hu
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
542018
Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement
Y Lin, Z Jiang, J Gu, W Li, S Dhar, H Ren, B Khailany, DZ Pan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
502020
Converged large block and structured synthesis for high performance microprocessor designs
M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ...
US Patent 8,271,920, 2012
472012
Computational geometry based placement migration
T Luo, H Ren, CJ Alpert, DZ Pan
ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005
422005
High performance graph convolutional networks with applications in testability analysis
Y Ma, H Ren, B Khailany, H Sikka, L Luo, K Natarajan, B Yu
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
412019
History-based VLSI legalization using network flow
M Cho, H Ren, H Xiang, R Puri
Proceedings of the 47th Design Automation Conference, 286-291, 2010
322010
Clock aware placement
CJ Alpert, DJ Hathaway, WR Migatz, GJ Nam, H Ren, PG Villarrubia
US Patent 7,624,366, 2009
302009
Hippocrates: First-do-no-harm detailed placement
H Ren, DZ Pan, CJ Alpert, GJ Nam, P Villarrubia
2007 Asia and South Pacific Design Automation Conference, 141-146, 2007
262007
True crosstalk aware incremental placement with noise map
H Ren, DZ Pan, PG Villarubia
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004
262004
Low cost test point insertion without using extra registers for high performance design
H Ren, M Kusko, V Kravets, R Yaari
2009 International Test Conference, 1-8, 2009
252009
A brief introduction on contemporary high-level synthesis
H Ren
2014 IEEE International Conference on IC Design & Technology, 1-4, 2014
232014
Integrated circuit design changes using through-silicon vias
H Barowski, J Keinert, SH Rangarajan, H Ren, S Saha
US Patent 9,501,603, 2016
222016
Method for successive placement based refinement of a generalized cost function
H Ren, P Villarrubia, ZM Kurzum, S Ramji
US Patent 7,076,755, 2006
222006
Constrained detailed placement
CJ Alpert, GJ Nam, H Ren, PG Villarrubia
US Patent 7,467,369, 2008
182008
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