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Sushmita Rao
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Estimating Power Supply Noise and its impact on path delay
SK Rao, C Sathyanarayana, A Kallianpur, R Robucci, C Patel
VLSI Test Symposium (VTS), 2012 IEEE 30th, 276-281, 2012
152012
Scalable dynamic technique for accurately predicting power-supply noise and path delay
SK Rao, R Robucci, C Patel
VLSI Test Symposium (VTS), 2013 IEEE 31st, 1-6, 2013
142013
Post-layout estimation of side-channel power supply signatures
SK Rao, D Krishnankutty, R Robucci, N Banerjee, C Patel
Hardware Oriented Security and Trust (HOST), 2015 IEEE International …, 2015
102015
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
SK Rao, R Robucci, C Patel
Journal of Electronic Testing 30 (1), 125-147, 2014
72014
Estimation of dynamic current waveforms using pre-characterization of standard cells
B Shivashankar, M Skaggs, SK Rao, R Robucci, N Banerjee, C Patel
Test Symposium (LATS), 2015 16th Latin-American, 1-6, 2015
22015
Scalability study of PSANDE: Power supply analysis for noise and delay estimation
SK Rao, B Shivashankar, R Robucci, N Banerjee, C Patel
VLSI Test Symposium (VTS), 2015 IEEE 33rd, 1-6, 2015
12015
Framework for dynamic estimation of power-supply noise and path delay
SK Rao, R Robucci, C Patel
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2013 …, 2013
12013
Transient current estimation using S3C (Standard cell current transient characterization)
M Skaggs, SK Rao, R Robucci, N Banerjee, C Patel
VLSI Design and Test (VDAT), 2015 19th International Symposium on, 1-6, 2015
2015
PSANDE: Framework for Accurate Dynamic Power Supply Analysis for Noise and Delay Estimation
SK Rao
University of Maryland, Baltimore County, 2015
2015
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Articles 1–9