| Loihi: A neuromorphic manycore processor with on-chip learning M Davies, N Srinivasa, TH Lin, G Chinya, Y Cao, SH Choday, G Dimou, ... Ieee Micro 38 (1), 82-99, 2018 | 3151 | 2018 |
| Design and analysis of an approximate adder with hybrid error reduction H Seo, YS Yang, Y Kim Electronics 9 (3), 471, 2020 | 47 | 2020 |
| Parallel and pipeline processing for block cipher algorithms on a network-on-chip YS Yang, JH Bahn, SE Lee, N Bagherzadeh 2009 Sixth International Conference on Information Technology: New …, 2009 | 39 | 2009 |
| Low-power, resilient interconnection with orthogonal latin squares SE Lee, YS Yang, GS Choi, W Wu, R Iyer IEEE Design & Test of Computers 28 (2), 30-39, 2011 | 33 | 2011 |
| A generic network interface architecture for a networked processor array (NePA) SE Lee, JH Bahn, YS Yang, N Bagherzadeh Architecture of Computing Systems–ARCS 2008: 21st International Conference …, 2008 | 30 | 2008 |
| On design and application mapping of a Network-on-Chip (NoC) architecture JH Bahn, SE Lee, YS Yang, J Yang, N Bagherzadeh Parallel Processing Letters 18 (02), 239-255, 2008 | 27 | 2008 |
| Recent trend of neuromorphic computing hardware: Intel's neuromorphic system perspective YS Yang, Y Kim 2020 International SoC Design Conference (ISOCC), 218-219, 2020 | 20 | 2020 |
| WaveSync: A low-latency source synchronous bypass network-on-chip architecture YS Yang, R Kumar, G Choi, P Gratz Computer Design (ICCD), 2012 IEEE 30th International Conference on, 241-248, 2012 | 15 | 2012 |
| An energy-efficient imprecise adder with a lower-part constant approximation H Seo, YS Yang, Y Kim 2020 International SoC Design Conference (ISOCC), 143-144, 2020 | 9 | 2020 |
| SDPR: Improving latency and bandwidth in on-chip interconnect through simultaneous dual-path routing YS Yang, H Deshpande, G Choi, PV Gratz IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016 | 9 | 2016 |
| Approximate digital leaky integrate-and-fire neurons for energy efficient spiking neural networks YS Yang, Y Kim IEIE Transactions on Smart Processing & Computing 9 (3), 252-259, 2020 | 8 | 2020 |
| Intra-flit skew reduction for asynchronous bypass channel in nocs R Kumar, YS Yang, G Choi 2011 24th Internatioal Conference on VLSI Design, 238-243, 2011 | 7 | 2011 |
| Method and apparatus for storing/reproducing transport stream, and digital receiver using the same YS Yang US Patent 7,424,038, 2008 | 5 | 2008 |
| Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router YS Yang, H Deshpande, G Choi, P Gratz 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2433-2436, 2012 | 4 | 2012 |
| Apparatus for encrypting/decrypting real-time input stream YS Yang US Patent 7,783,036, 2010 | 3 | 2010 |
| Unequal error protection based on DVFS for JSCD in low-power portable multimedia systems YS Yang, G Choi ACM Transactions on Embedded Computing Systems (TECS) 11 (2), 1-21, 2012 | 2 | 2012 |
| Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system YS Yang, P Bhagawat, G Choi Proceedings of the 48th Design Automation Conference, 579-584, 2011 | 2 | 2011 |
| Low-power baseband processing for wireless multimedia systems using unequal error protection YS Yang, G Choi 2010 Wireless Telecommunications Symposium (WTS), 1-6, 2010 | 2 | 2010 |
| Parallel processing for block ciphers on a fault tolerant networked processor array YS Yang, JH Bahn, SE Lee, J Yang, N Bagherzadeh International Journal of High Performance Systems Architecture 2 (3-4), 156-167, 2010 | 2 | 2010 |
| Low-Power Cross-Layer Error Management Using MIMO-LDPC Iterative Decoding for Video Processing YS Yang, Y Kim IEEE Access 9, 133062-133075, 2021 | 1 | 2021 |
