Jean Pierre David
Jean Pierre David
Professeur en génie électrique, Polytechnique Montréal
Verified email at polymtl.ca - Homepage
Title
Cited by
Cited by
Year
Binaryconnect: Training deep neural networks with binary weights during propagations
M Courbariaux, Y Bengio, JP David
Advances in Neural Information Processing Systems, 3123-3131, 2015
16122015
Training deep neural networks with low precision multiplications
M Courbariaux, Y Bengio, JP David
arXiv preprint arXiv:1412.7024, 2014
3462014
Low precision arithmetic for deep learning.
M Courbariaux, Y Bengio, JP David
ICLR (Workshop), 2015
2122015
A state-space modeling approach for the FPGA-based real-time simulation of high switching frequency power converters
HF Blanchette, T Ould-Bachir, JP David
IEEE Transactions on Industrial Electronics 59 (12), 4555-4567, 2012
782012
Hardware complexity of modular multiplication and exponentiation
JP David, K Kalach, N Tittley
IEEE Transactions on Computers 56 (10), 1308-1319, 2007
432007
A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration
MA Daigneault, JP David
IEEE transactions on instrumentation and measurement 60 (6), 2070-2079, 2011
372011
An Evaluation of a High-Level Synthesis Approach to the FPGA-Based Submicrosecond Real-Time Simulation of Power Converters
F Montano, T Ould-Bachir, JP David
IEEE Transactions on Industrial Electronics 65 (1), 636-644, 2018
362018
A fully automated reconfigurable calculation engine dedicated to the real-time simulation of high switching frequency power electronic circuits
TO Bachir, C Dufour, J Bélanger, J Mahseredjian, JP David
Mathematics and Computers in Simulation 91, 167-177, 2013
352013
Effective FPGA-based electric motor modeling with floating-point cores
TO Bachir, JP David, C Dufour, J Bélanger
IECON 2010-36th Annual Conference on IEEE Industrial Electronics Society …, 2010
342010
A cryptanalytic time-memory tradeoff: First FPGA implementation
Q Jean-Jacques, S Francois-Xavier, G Rouvroy, D Jean-Pierre, ...
International Conference on Field Programmable Logic and Applications, 780-789, 2002
292002
. NET framework-a solution for the next generation tools for system-level modeling and simulation
J Lapalme, EM Aboulhamid, G Nicolescu, L Charest, FR Boyer, JP David, ...
Proceedings Design, Automation and Test in Europe Conference and Exhibition …, 2004
282004
A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA
MA Daigneault, JP David
Proceedings of the 8th IEEE International NEWCAS Conference 2010, 281-284, 2010
272010
Effective floating-point calculation engines intended for the FPGA-based HIL simulation
T Ould-Bachir, C Dufour, J Bélanger, J Mahseredjian, JP David
2012 IEEE International Symposium on Industrial Electronics, 1363-1368, 2012
252012
Generic crossbar network on chip for FPGA MPSoCs
D Bafumba-Lokilo, Y Savaria, JP David
2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems …, 2008
252008
ESys. Net: a new solution for embedded systems modeling and simulation
J Lapalme, EM Aboulhamid, G Nicolescu, L Charest, FR Boyer, JP David, ...
ACM SIGPLAN Notices 39 (7), 107-114, 2004
232004
Performing floating-point accumulation on a modern FPGA in single and double precision
TO Bachir, JP David
2010 18th IEEE Annual International Symposium on Field-Programmable Custom …, 2010
222010
Hardware implementation of large number multiplication by FFT with modular arithmetic
K Kalach, JP David
The 3rd International IEEE-NEWCAS Conference, 2005., 267-270, 2005
212005
Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA
E Bergeron, M Feeley, MA Daigneault, JP David
2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems …, 2008
172008
FPGA-based real-time simulation of state-space models using floating-point cores
TO Bachir, JP David
Proceedings of 14th International Power Electronics and Motion Control …, 2010
162010
An Intermediate Level HDL for System Level Design.
JP David, E Bergeron
FDL 4, 526-36, 2004
162004
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Articles 1–20