| Lack of spatial correlation in MOSFET threshold voltage variation and implications for voltage scaling N Drego, A Chandrakasan, D Boning IEEE Transactions on Semiconductor Manufacturing 22 (2), 245-255, 2009 | 62 | 2009 |
| Variation DS Boning, K Balakrishnan, H Cai, N Drego, A Farahanchi, KM Gettings, ... IEEE Transactions on Semiconductor Manufacturing 21 (1), 63-71, 2008 | 56 | 2008 |
| A test-structure to efficiently study threshold-voltage variation in large MOSFET arrays N Drego, A Chandrakasan, D Boning 8th International Symposium on Quality Electronic Design (ISQED'07), 281-286, 2007 | 52 | 2007 |
| All-digital circuits for measurement of spatial variation in digital circuits N Drego, A Chandrakasan, D Boning IEEE Journal of Solid-State Circuits 45 (3), 640-651, 2010 | 37 | 2010 |
| Reduction of variation-induced energy overhead in multi-core processors N Drego, A Chandrakasan, D Boning, D Shah IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2011 | 12 | 2011 |
| An all-digital, highly scalable architecture for measurement of spatial variation in digital circuits N Drego, A Chandrakasan, D Boning 2008 IEEE Asian Solid-State Circuits Conference, 393-396, 2008 | 10 | 2008 |
| Characterization and mitigation of process variation in digital circuits and systems NA Drego Massachusetts Institute of Technology, 2009 | 6 | 2009 |
| A low-skew, low jitter receiver circuit for on-chip optical clock distribution NA Drego Massachusetts Institute of Technology, 2003 | 5 | 2003 |
| Lack of spatial correlation in mosfet threshold voltage variation and implications for voltage scaling DS Boning, NA Drego, AP Chandrakasan Institute of Electrical and Electronics Engineers, 2013 | | 2013 |
| Spatial Variation in Advanced CMOS Devices and Circuits N Drego, AP Chandrakasan, DS Boning Circuits & Systems, 4, 2005 | | 2005 |
| RM/sup 3/integration of InP based 1.55/spl mu/m PiN photodetectors with silicon CMOS optical clock distribution circuits E Atmaca, V Lei, M Teo, N Drego, D Boning, CG Fonstad, LW Khai, ... 2003 International Symposium on Compound Semiconductors: Post-Conference …, 2003 | | 2003 |
| RM/sup 3/integration of indium phosphide based 1.55/spl mu/m pin photodetectors with silicon CMOS optical clock receiver circuits E Atmaca, N Drego, D Boning, CG Fonstad, LW Khai, YS Fatt 2003 International Symposium on Compound Semiconductors, 197-198, 2003 | | 2003 |
| Design and Variation Analysis of an On-Chip Optical Clock Receiver Circuit N Drego, A Lum | | |
| Test Structures and Optimization Methodologies for Electrical Variation in IC Manufacturing K Balakrishnan, N Drego, K Gettings, D Lim, DS Boning CIRCUITS & SYSTEMS, 1, 0 | | |
| Prediction of Variation in Advanced Process Technology Nodes N Drego, AP Chandrakasan, D Boning | | |
Duane BoningMassachusetts Institute of TechnologyVerified email at mtl.mit.edu
