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Yu-Shih Su
Yu-Shih Su
Verified email at mediatek.com
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Cited by
Cited by
Year
Performance optimization using variable-latency design style
YS Su, DC Wang, SC Chang, M Marek-Sadowska
IEEE transactions on very large scale integration (VLSI) systems 19 (10 …, 2010
582010
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
YS Su, WK Hon, CC Yang, SC Chang, YJ Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
342010
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
YS Su, WK Hon, CC Yang, SC Chang, YJ Chang
2009 IEEE/ACM International Conference on Computer-Aided Design-Digest of …, 2009
342009
Through-silicon via fault-tolerant clock networks for 3-D ICs
CL Lung, YS Su, HH Huang, Y Shi, SC Chang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013
292013
An efficient mechanism for performance optimization of variable-latency designs
YS Su, DC Wang, SC Chang, M Marek-Sadowska
Proceedings of the 44th annual Design Automation Conference, 976-981, 2007
282007
Fault-tolerant 3D clock network
CL Lung, YS Su, SH Huang, Y Shi, SC Chang
Proceedings of the 48th Design Automation Conference, 645-651, 2011
262011
Fault-tolerant unit and method for through-silicon via
CL Lung, YS Su, SC Chang, Y Shi
US Patent 9,177,940, 2015
182015
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
PW Luo, C Zhang, YT Chang, LC Cheng, HH Lee, BL Sheu, YS Su, ...
Proceedings of the 2013 ACM International symposium on Physical Design, 17-24, 2013
112013
Capturing the phantom of the power grid-on the runtime adaptive techniques for noise reduction
T Wang, PW Luo, YS Su, LC Cheng, DM Kwai, Y Shi
17th Asia and South Pacific Design Automation Conference, 640-645, 2012
62012
Synthesis of a novel timing-error detection architecture
YS Su, PH Chang, SC Chang, T Hwang
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (1 …, 2008
52008
Efficient calculation of timed cumulative probability density function
YS Su, YH Weng, SC Chang
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2007
12007
Synthesis of a timing-error detection architecture
YS Su, PH Chang, SC Chang, TT Hwang
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI …, 2008
2008
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