Mehdi Modarressi
TitleCited byYear
Application-aware topology reconfiguration for on-chip networks
M Modarressi, A Tavakkol, H Sarbazi-Azad
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (11), 2010
992010
Virtual point-to-point connections for NoCs
M Modarressi, A Tavakkol, H Sarbazi-Azad
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
682010
A hybrid packet-circuit switched on-chip network based on SDM
M Modarressi, H Sarbazi-Azad, M Arjomand
2009 Design, Automation & Test in Europe Conference & Exhibition, 566-569, 2009
642009
Power-aware mapping for reconfigurable NoC architectures
M Modarressi, H Sarbazi-Azad
2007 25th International Conference on Computer Design, 417-422, 2007
362007
An efficient dynamically reconfigurable on-chip network architecture
M Modarressi, H Sarbazi-Azad, A Tavakkol
Design Automation Conference, 166-169, 2010
302010
An energy-efficient virtual channel power-gating mechanism for on-chip networks
A Mirhosseini, M Sadrosadati, A Fakhrzadehgan, M Modarressi, ...
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
262015
An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
P Lotfi-Kamran, M Modarressi, H Sarbazi-Azad
IEEE Transactions on Computers, 0
21*
Fast data delivery for many-core processors
M Bakhshalipour, P Lotfi-Kamran, A Mazloumi, F Samandi, ...
IEEE Transactions on Computers 67 (10), 1416-1429, 2018
162018
A reconfigurable cache architecture for object-oriented embedded systems
M Modarressi, S Hessabi, M Goudarzi
2006 Canadian Conference on Electrical and Computer Engineering, 959-962, 2006
162006
Reconfigurable communication fabric for efficient implementation of neural networks
A Firuzan, M Modarressi, M Daneshtalab
2015 10th International Symposium on Reconfigurable Communication-centric …, 2015
152015
Near-ideal networks-on-chip for servers
P Lotfi-Kamran, M Modarressi, H Sarbazi-Azad
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
142017
Power and performance efficient partial circuits in packet-switched networks-on-chip
N Teimouri, M Modarressi, H Sarbazi-Azad
2013 21st Euromicro International Conference on Parallel, Distributed, and …, 2013
142013
Power-efficient accelerator design for neural networks using computation reuse
A Yasoubi, R Hojabr, M Modarressi
IEEE Computer Architecture Letters 16 (1), 72-75, 2016
132016
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
M Modarressi, H Sarbazi-Azad, A Tavakkol
2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 203-212, 2009
12*2009
Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip
S Rezaei, S Hossein, A Mazloumi, M Modarressi, P Lotfi-Kamran
IEEE Computer Architecture Letters, 0
12*
A load-balanced routing scheme for noc-based systems-on-chip
MA Yazdi, M Modarressi, H Sarbazi-Azad
2010 First Workshop on Hardware and Software Implementation and Control of …, 2010
112010
An SDM-based hybrid packet-circuit-switched on-chip network
M Modarressi, H Sarbazi-Azad, M Arjomand
Proc. of DATE, 2009
112009
The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks
R Sabbaghi-Nadooshan, M Modarressi, H Sarbazi-Azad
2008 IEEE International Conference on Computer Design, 486-490, 2008
112008
A novel high-performance and low-power mesh-based NoC
R Sabbaghi-Nadooshan, M Modarressi, H Sarbazi-Azad
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-7, 2008
112008
A hybrid packet/circuit-switched router to accelerate memory access in NoC-based chip multiprocessors
A Mazloumi, M Modarressi
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 908-911, 2015
102015
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Articles 1–20