| Methods, apparatus and system to support large-scale micro-systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical … Y Blaquière, Y Savaria, Y Basile-Bellavance, O Valorge, A Lahkssassi, ... US Patent App. 13/782,868, 2013 | 77 | 2013 |
| An active reconfigurable circuit board R Norman, O Valorge, Y Blaquière, E Lepercq, Y Basile-Bellavance, ... 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems …, 2008 | 43 | 2008 |
| Methods, apparatus, and systems for reducing interference on nearby conductors K Fecteau, C Thibeault, Y Savaria, Y Blaquiere, JJ Laurin, ZF Jin US Patent 7,609,778, 2009 | 28 | 2009 |
| Methods, apparatus, and systems for reducing interference on nearby conductors Y Savaria, Y Blaquiere US Patent 6,703,868, 2004 | 27 | 2004 |
| Acceleration of the secure hash algorithm-256 (SHA-256) on an FPGA-CPU cluster using OpenCL H Bensalem, Y Blaquière, Y Savaria 2021 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2021 | 14 | 2021 |
| A versatile 200-V capacitor-coupled level shifter for fully floating multi-MHz gate drivers VH Nguyen, N Ly, AH Alameh, Y Blaquière, G Cowan IEEE Transactions on Circuits and Systems II: Express Briefs 68 (5), 1625-1629, 2021 | 14 | 2021 |
| An interconnection network for a novel reconfigurable circuit board E Lepercq, O Valorge, Y Basile-Bellavance, N Laflamme-Mayer, ... 2009 2nd Microsystems and Nanoelectronics Research Conference, 53-56, 2009 | 14 | 2009 |
| A high voltage multi-purpose on-the-fly reconfigurable half-bridge gate driver for GaN HEMTs in 0.18-μm HV SOI CMOS technology N Ly, N Aimaier, AH Alameh, Y Blaquière, G Cowan, NG Constantin 2020 18th IEEE International New Circuits and Systems Conference (NEWCAS …, 2020 | 13 | 2020 |
| Faults diagnosis methodology for the WaferNet interconnection network Y Basile-Bellavance, Y Blaquière, Y Savaria 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA …, 2009 | 13 | 2009 |
| Workflow for an electronic configurable prototyping system E Lepercq, Y Blaquière, R Norman, Y Savaria 2009 IEEE International Symposium on Circuits and Systems, 2005-2008, 2009 | 13 | 2009 |
| On extra combinational delays in SRAM FPGAs due to transient ionizing radiations C Thibeault, S Pichette, Y Audet, Y Savaria, H Rufenacht, E Gloutnay, ... IEEE Transactions on Nuclear Science 59 (6), 2959-2965, 2012 | 12 | 2012 |
| A VLSI architecture for fast clustering with fuzzy ART neural networks E Granger, Y Blaquière, Y Savaria, MA Cantin, P Lavoie Proceedings of International Workshop on Neural Networks for Identification …, 1996 | 12 | 1996 |
| Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain Y Blaquière, Y Basile-Bellavance, S Berrima, Y Savaria 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2559-2562, 2014 | 11 | 2014 |
| Evaluation of anisotropic conductive films based on vertical fibers for post-CMOS wafer-level packaging MD Diop, M Radji, AA Hamoui, Y Blaquière, R Izquierdo IEEE Transactions on Components, Packaging and Manufacturing Technology 3 (4 …, 2013 | 11 | 2013 |
| An interconnection network for a novel reconfigurable circuit board R Norman, E Lepercq, Y Blaquière, O Valorge, Y Basile-Bellavance, ... 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems …, 2008 | 11 | 2008 |
| A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array S Berrima, Y Blaquière, Y Savaria 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 10 | 2017 |
| Implementation of the fuzzy ART neural network for fast clustering of radar pulses MA Cantin, Y Blaquière, Y Savaria, E Granger, P Lavoie ISCAS'98. Proceedings of the 1998 IEEE International Symposium on Circuits …, 1998 | 10 | 1998 |
| Circuit level modeling of extra combinational delays in SRAM-based FPGAs due to transient ionizing radiation M Darvishi, Y Audet, Y Blaquiere, C Thibeault, S Pichette, FZ Tazi IEEE Transactions on Nuclear Science 61 (6), 3535-3542, 2014 | 9 | 2014 |
| Electrical characterization of annular through silicon vias for a reconfigurable wafer-sized circuit board MD Diop, M Radji, W Andre, Y Blaquière, AA Hamoui, R Izquierdo 19th Topical Meeting on Electrical Performance of Electronic Packaging and …, 2010 | 8 | 2010 |
| Fast timing analysis of VLSI circuits: a dynamic and hierarchical approach Y Blaquiere, M Dagenais, Y Savaria 1991., IEEE International Sympoisum on Circuits and Systems, 2398-2402, 1991 | 8 | 1991 |
