| Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout B Doyle, B Boyanov, S Datta, M Doczy, S Hareland, B Jin, J Kavalieros, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003 | 344 | 2003 |
| Strained transistor integration for CMOS B Boyanov, A Murthy, BS Doyle, R Chau US Patent 7,662,689, 2010 | 142 | 2010 |
| Method of making a semiconductor transistor AS Murthy, B Boyanov, R Soman, RS Chau US Patent 6,812,086, 2004 | 134 | 2004 |
| Transistor gate electrode having conductor material layer A Murthy, B Boyanov, S Datta, BS Doyle, BY Jin, S Yu, R Chau US Patent 7,223,679, 2007 | 116 | 2007 |
| Method for improving transistor performance through reducing the salicide interface resistance A Murthy, B Boyanov, GA Glass, T Hoffmann US Patent 6,949,482, 2005 | 106 | 2005 |
| Re-investigation of titanium silicalite by X-ray absorption spectroscopy: are the novel titanium sites real? S Pei, GW Zajac, JA Kaduk, J Faber, BI Boyanov, D Duck, D Fazzini, ... Catalysis letters 21 (3), 333-344, 1993 | 105 | 1993 |
| Double-gate transistor with enhanced carrier mobility B Boyanov, B Doyle, J Kavalieros, A Murthy, R Chau US Patent 6,974,733, 2005 | 90 | 2005 |
| Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer A Murthy, R Soman, B Boyanov US Patent 6,723,622, 2004 | 81 | 2004 |
| Silicon nano-transistors for logic applications R Chau, B Boyanov, B Doyle, M Doczy, S Datta, S Hareland, B Jin, ... Physica E: Low-dimensional systems and nanostructures 19 (1-2), 1-5, 2003 | 74 | 2003 |
| Estimation of measurement uncertainties in XAFS data M Newville, BI Boyanov, DE Sayers Journal of synchrotron radiation 6 (3), 264-265, 1999 | 62 | 1999 |
| X-ray photoelectron spectroscopy measurement of the Schottky barrier at the SiC (N)/Cu interface SW King, M French, M Jaehnig, M Kuhn, B Boyanov, B French Journal of Vacuum Science & Technology B, Nanotechnology and …, 2011 | 60 | 2011 |
| Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer A Murthy, R Soman, B Boyanov US Patent App. 10/448,817, 2003 | 56 | 2003 |
| Dielectric spacers for metal interconnects and method to form the same JD Bielefeld, B Boyanov US Patent 7,772,702, 2010 | 44 | 2010 |
| Method for improving transistor performance through reducing the salicide interface resistance A Murthy, B Boyanov, GA Glass, T Hoffmann US Patent 7,274,055, 2007 | 43 | 2007 |
| Fabricating strained channel epitaxial source/drain transistors A Murthy, JK Brask, AN Westmeyer, B Boyanov, N Lindert US Patent 7,226,842, 2007 | 41 | 2007 |
| Reducing internal film stress in dielectric film G Kloster, B Boyanov, M Goodner, M Moinpour, M Haverty US Patent App. 11/096,678, 2006 | 40 | 2006 |
| Forming a porous dielectric layer and structures formed thereby B Boyanov, GM Kloster, V Ramachandrarao, HM Park US Patent 7,179,755, 2007 | 39 | 2007 |
| Biochemically activated electronic device B Boyanov, JG Mandell, J Bai, KL Gunderson, CY Chen, M Perbost US Patent 10,605,766, 2020 | 33 | 2020 |
| Dielectric spacers for metal interconnects and method to form the same MA Hussein, B Boyanov US Patent 7,649,239, 2010 | 32 | 2010 |
| On‐Wafer Crystallization of Ultralow‐κ Pure Silica Zeolite Films Y Liu, CM Lew, M Sun, R Cai, J Wang, G Kloster, B Boyanov, Y Yan Angewandte Chemie 121 (26), 4871-4874, 2009 | 32 | 2009 |
Suman DattaStinson Chair ProfessorVerified email at nd.edu
